ASIC project integrating RV32 RISC-V with AXI4/AXI4-Lite accelerators for matrix inversion and CNNs. Developed using Verilog, Python, C/C++, Ripes, RARS, xPack, GCC, Lattice Diamond, Cadence, and Vivado for simulation, synthesis, and FPGA prototyping. - View it on GitHub