An optimized FPGA hardware-software co-design on the Zybo Z7 (Zynq-7010). Features a custom 16-PE pipelined Verilog array, 64-bit AXI-Stream DMA, banked BRAM ping-pong buffers, and a background prefetcher. Achieves a 5.15x speedup over a bare-metal ARM Cortex-A9 software baseline. - View it on GitHub