Using Core generator Designed and Verified functionality of following blocks i. 5x5 unsigned multiplier ii. 32x4 Simple Dual Port Ram iii. 5 Bit Adder/Subtractor Circuit using Fabric(Verify using FPGA Editor) iv. 3 Bit Adder/Subtractor Circuit using DSP48(Verify using FPGA Editor) v. 8x8 ROM with initial value provided from .coe file - View it on GitHub