Verilog/SystemVerilog models and examples for the AMD/Xilinx DSP48E1 slice used in 7-Series FPGAs (Artix-7, Kintex-7, Virtex-7, Zynq-7000). The DSP48E1 is a hardened arithmetic block supporting 25×18 multiplication, 48-bit accumulation, pre-addition (A+D), SIMD modes, pattern detection, and cascade chaining. - View it on GitHub