This work describes the implementation of a mini ULA that receives as input two 8-bit vectors as operands (called "A" and "B"), a selector vector of 5 bits (called "Selector") that allows the realization of up to 32 operations, and has an output of a 16-bit vector (called "O"). The language used was the description in VHDL using the software Quartus II and FPGA board D2-E, and Altera Up to carry out the simulations. We performed 17 operations that are described in the Control Unit of README. - View it on GitHub